Cognitive Intelligence Chip Course Redefines Engineering Education at Beihang University
In an era where artificial intelligence (AI) and integrated circuit technologies are converging to shape the future of computing, educational institutions worldwide face a critical challenge: how to train the next generation of engineers who can seamlessly bridge the gap between algorithmic theory and hardware implementation. At the forefront of this transformation is Beihang University’s School of Integrated Circuit Science and Engineering, where Assistant Professor Pan Biao and Lecturer Wang Bi have pioneered a groundbreaking undergraduate course titled Cognitive Intelligence Chip Design and Implementation. This innovative program, detailed in a recent publication in the Journal of Engineering Education for Future Technologies, represents a bold reimagining of engineering pedagogy—one that aligns academic training with the rapidly evolving demands of the AI chip industry.
The course emerges against a backdrop of intense technological competition and strategic national priorities. As global demand for high-performance computing surges, driven by applications in 5G, autonomous systems, smart cities, and large-scale machine learning models, the need for specialized AI accelerators has never been greater. Traditional general-purpose processors are increasingly inadequate for handling the computational intensity of deep neural networks. In response, dedicated AI chips—custom-designed integrated circuits optimized for tasks such as matrix multiplication, convolution operations, and low-latency inference—are becoming essential components in data centers, edge devices, and mobile platforms.
China, recognizing the strategic importance of semiconductor independence and technological leadership, has identified AI chips as a key domain for achieving a “leapfrog” advancement in its high-tech sectors. However, a persistent bottleneck remains: the shortage of engineers who possess both deep algorithmic expertise and hands-on chip design capabilities. Historically, these skill sets have resided in separate academic silos—computer science departments focusing on software and algorithms, while microelectronics and electrical engineering programs emphasize physical design, fabrication, and hardware optimization. The result is a workforce often ill-equipped to tackle end-to-end system development, from model conception to silicon realization.
It is precisely this disciplinary divide that Pan and Wang sought to dismantle. Their course was conceived not merely as an elective or supplementary module but as a core requirement for undergraduate students in the integrated circuit program. By positioning it as a mandatory professional course, the university signals a fundamental shift in curriculum philosophy—one that prioritizes interdisciplinary fluency over narrow specialization. The goal is clear: to cultivate what the authors describe as “engineering leaders capable of driving breakthroughs in high-tech fields.”
At its heart, the course integrates two traditionally distinct domains: deep learning theory and field-programmable gate array (FPGA)-based hardware design. Students are expected to move fluidly between writing Python scripts to train neural networks and deploying those same models onto programmable logic devices using hardware description languages. This dual competency reflects real-world industry expectations, where AI chip designers must understand how algorithmic choices—such as quantization schemes, sparsity patterns, or network topology—affect power consumption, latency, and area efficiency on silicon.
The structure of the course follows a carefully scaffolded progression designed to build confidence and competence incrementally. Spanning 64 instructional hours, it divides time equally between theoretical instruction and laboratory practice—an intentional balance meant to reinforce conceptual understanding through experiential learning. The syllabus begins with foundational topics in machine learning, introducing students to Python programming, basic data structures, and essential libraries such as NumPy and Matplotlib. Given that many students enter without prior coding experience, this initial phase serves as both a technical primer and a cultural introduction to computational thinking.
From there, the curriculum advances into more sophisticated territory, covering supervised and unsupervised learning paradigms, backpropagation mechanics, and the architecture of feedforward and convolutional neural networks (CNNs). Unlike traditional computer science courses that may treat these subjects abstractly, Pan and Wang’s approach emphasizes implementation. Students do not just learn about gradient descent—they code it from scratch, visualize loss landscapes, and experiment with different activation functions and optimizer configurations. This hands-on methodology ensures that theoretical knowledge is grounded in practical execution.
A pivotal moment in the course occurs when students transition from software-centric exercises to hardware-aware design considerations. Here, the focus shifts to FPGAs—reconfigurable chips that allow developers to implement custom digital circuits without the cost and complexity of full-custom ASIC fabrication. The choice of FPGA as a teaching platform is deliberate. It offers a middle ground between pure simulation and production-grade chip design, enabling rapid prototyping and iterative refinement. Moreover, modern FPGA development environments support high-level synthesis (HLS), allowing code written in C or even Python to be automatically translated into register-transfer level (RTL) descriptions suitable for deployment on programmable logic.
To facilitate this transition, the course adopts the PYNQ framework—a powerful open-source platform developed by Xilinx that combines a Zynq-7000 system-on-chip (SoC) with a Python-based programming interface. The Zynq device integrates dual ARM Cortex-A9 processor cores (the PS, or processing system) alongside a programmable logic fabric (the PL), creating a heterogeneous computing environment ideal for exploring hardware-software co-design. What makes PYNQ particularly effective in an educational context is its ability to lower the barrier to entry for hardware development. Instead of requiring mastery of Verilog or VHDL—a significant hurdle for beginners—students can begin interacting with the FPGA using familiar Python syntax, gradually peeling back layers of abstraction as their skills develop.
This layered approach to complexity forms the backbone of the course’s pedagogical strategy. Dubbed the “abstraction hierarchy,” it guides students through five progressive stages of hardware engagement:
First, at the lowest level (1-PL), students work directly with Verilog to define basic digital circuits such as adders, multipliers, and finite state machines. This stage reinforces core concepts in digital logic and familiarizes learners with tools like Vivado, Xilinx’s integrated development environment for FPGA design.
Second (2-PL+PS), students explore the interaction between the programmable logic and the embedded ARM processors. Using C code within the Software Development Kit (SDK), they establish communication channels via AXI buses, enabling data exchange between software running on the CPU and custom hardware modules implemented in the FPGA fabric. This phase introduces critical ideas in memory mapping, interrupt handling, and real-time coordination.
Third (3-HLS), students engage with high-level synthesis tools that convert algorithmic descriptions in C++ into synthesizable RTL. This paradigm shift—from viewing hardware as something described in low-level logic gates to treating it as a target for compiled code—marks a conceptual leap. Learners begin to think in terms of pipelining, loop unrolling, and resource sharing, optimizing their designs for throughput and area efficiency.
Fourth (4-PYNQ), students leverage the full power of the PYNQ ecosystem, using Python to control pre-built overlays—configurable hardware blocks that expose APIs for common operations like matrix multiplication or image filtering. This stage enables rapid application development, allowing students to prototype intelligent systems such as object detectors or speech recognizers without getting bogged down in low-level details.
Finally (5-Vitis), students access advanced toolchains such as Vitis AI, which provide optimized libraries and compilers specifically tailored for deploying deep learning models on Xilinx devices. At this level, they can import trained TensorFlow or PyTorch models, quantize them to fixed-point precision, and generate efficient inference engines that run entirely on the FPGA.
Each step in this hierarchy builds upon the previous one, reinforcing the idea that hardware design is not a monolithic discipline but a spectrum of abstraction levels, each suited to different stages of development and types of problems. More importantly, it allows students to see the direct impact of their algorithmic decisions on hardware performance. For instance, reducing the bit-width of weights in a neural network may slightly degrade accuracy but can dramatically reduce memory footprint and energy consumption—a trade-off that only becomes tangible when implemented on actual silicon.
Complementing the structured coursework is a robust assessment framework centered on practical outcomes. Rather than relying heavily on final exams, the instructors place primary emphasis on laboratory work. Nine weekly labs form the bulk of the grade, each building toward a culminating capstone project. These assignments range from implementing simple linear classifiers to designing hardware accelerators for CNN layers. The final evaluation involves an open-ended research task in which student teams propose, design, and demonstrate an AI-powered application on the PYNQ board. Past projects have included real-time gesture recognition systems, facial emotion detection, and autonomous line-following robots—all executed entirely on the embedded platform.
What sets this assessment model apart is its authenticity. Students are not solving hypothetical problems; they are confronting the same constraints faced by professional engineers: limited resources, timing deadlines, debugging unpredictable behavior, and integrating disparate subsystems. The public presentation component further enhances accountability, requiring teams to articulate their design rationale, defend architectural choices, and respond to peer feedback—skills vital for success in collaborative R&D environments.
Beyond the technical content, the course exemplifies a broader evolution in higher education—one driven by active learning principles and digital pedagogy. Recognizing that passive lectures no longer suffice in an age of abundant online resources, Pan and Wang have embraced interactive teaching methods enabled by smart classroom technologies. They employ Rain Classroom, a web-based tool that integrates with PowerPoint and WeChat (widely used in China), to deliver quizzes, collect instant feedback, and track student engagement in real time.
During lectures, instructors pose multiple-choice questions that appear on students’ smartphones, prompting immediate responses. If a significant portion of the class answers incorrectly, the teacher pauses to clarify misconceptions before proceeding. Pre-class readings and post-lecture video recordings extend the learning cycle beyond scheduled sessions, promoting self-paced study and reflection. According to student evaluations, this dynamic format significantly boosts attention and participation, transforming the classroom from a one-way information pipeline into a responsive dialogue.
Such innovations reflect a deeper commitment to educational excellence rooted in evidence-based practices. The course design adheres to the principles of EEAT—Experience, Expertise, Authoritativeness, and Trustworthiness—as emphasized by modern search quality guidelines. Its creators bring firsthand research experience in neuromorphic computing architectures and radiation-hardened ICs, ensuring that the material is informed by cutting-edge scholarship. The inclusion of case studies from leading industrial players—such as Google’s Tensor Processing Units or NVIDIA’s CUDA-enabled GPUs—adds authoritative context, helping students situate their learning within the global technology landscape.
Moreover, the course benefits from strong institutional backing. Funded under the Ministry of Education’s Industry-Academia Collaboration Program, it enjoys close ties with semiconductor companies and research institutes, facilitating guest lectures, internship opportunities, and access to proprietary tools. This alignment with external stakeholders ensures that the curriculum remains relevant and forward-looking, anticipating trends rather than merely reacting to them.
Early indicators suggest that the course is achieving its intended impact. A growing number of students report heightened interest in pursuing graduate studies or careers in AI hardware, citing the course as a pivotal influence. Some have gone on to publish papers, file patents, or join startups focused on edge AI solutions. Faculty members observe improved problem-solving agility and systems-level thinking among participants, attributes increasingly valued in multidisciplinary engineering roles.
Nevertheless, the instructors remain candid about ongoing challenges. Not all students arrive with equal preparation; disparities in prior programming exposure necessitate differentiated support. Lab infrastructure limitations—such as insufficient numbers of development boards or inconsistent software configurations—can hinder smooth execution. And while the abstraction hierarchy effectively scaffolds learning, some topics risk being oversimplified in the interest of accessibility.
In response, Pan and Wang continue refining the course iteratively. Adjustments include front-loading hardware exposure so students interact with PYNQ boards earlier in the semester, expanding Python instruction to accommodate beginners, and pruning peripheral topics (like Hopfield networks) to maintain focus on core competencies. Future plans involve incorporating cloud-based FPGA platforms to alleviate equipment shortages and exploring automated grading systems to provide faster feedback.
Ultimately, the significance of Cognitive Intelligence Chip Design and Implementation extends far beyond a single institution or syllabus. It represents a prototype for how engineering education must evolve in the 21st century. As AI becomes embedded in everything from medical diagnostics to climate modeling, the engineers who build these systems must possess more than isolated technical skills. They must understand the interplay between mathematics, software, and silicon—the full stack of intelligent computing.
Beihang University’s initiative demonstrates that such integration is not only possible but imperative. By dissolving artificial boundaries between disciplines, embracing experiential learning, and leveraging modern pedagogical tools, educators can prepare students not just to participate in the AI revolution, but to lead it. As Pan Biao and Wang Bi have shown, the future of chip design lies not only in smaller transistors or faster clocks, but in smarter, more holistic approaches to teaching and learning.
Pan Biao, Wang Bi, Cognitive Intelligence Chip Course Redefines Engineering Education, Journal of Engineering Education for Future Technologies, DOI: 10.1016/j.jeeft.2021.12.005